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module data_capture
(
    input clk,rstn,
    input in_vld,
    input[11:0] din,
    output reg out_vld,
    output reg[31:0] dout
);
parameter AVE_DATA_NUM = 3'd5;
/////////////////////Shift register///////////////////////////
reg [11:0] data_reg [AVE_DATA_NUM-1:0];
reg [3:0]temp_i;

always @ (posedge clk)
begin
    if(rstn || !in_vld)
        for (temp_i=0; temp_i<AVE_DATA_NUM; temp_i=temp_i 1)
            data_reg[temp_i] <= 'd0;
    else
    begin
        data_reg[0] <= din;
        for (temp_i=0; temp_i<AVE_DATA_NUM-1; temp_i=temp_i 1)
            data_reg[temp_i 1] <= data_reg[temp_i];
    end
end

/////////////////////sum//////////////////////////////
reg [31:0] sum;

always @ (posedge clk )
begin
    if (rstn || !in_vld)
        sum <= 'd0;
    else
        sum <= sum   din - data_reg[AVE_DATA_NUM-1]; //Replace the oldest data with the latest input data
end

////////////////////cnt////////////////////////////
reg[8:0] cnt;

always @(posedge clk)
begin
    if (rstn || !in_vld)
        cnt <= 'd0;
    else if(cnt == 9'd64)
        cnt <= 0;
    else
        cnt <= cnt   1'b1;
        
end

///////////////////dout////////////////////////////
always @(posedge clk)
begin
    if (rstn || !in_vld) begin
        dout <= 11'd0;
        out_vld <= 1'd0;
    end
    else if(cnt > 9'd4) begin
        out_vld <= 1'b1;
        dout <= sum>>2; //sum/4。
    end
    else begin
        out_vld <= 1'b0;
        dout    <= 0;
    end
end    


endmodule

`timescale 1ns/1ns

module capture_tb();

reg clk,rstn;
reg in_vld;
reg[11:0] din;

wire out_vld;
wire[31:0] dout;


initial begin
    clk = 1;
    rstn = 1;
    in_vld = 0;
    #200
        rstn = 0;
        in_vld = 1;
    #10000
    $stop();
end

always #10 clk = ~clk;

always #20 din = {$random}%100;

data_capture tb(
    .clk(clk),.rstn(rstn),
    .in_vld(in_vld),
    .din(din),
    .out_vld(out_vld),
    .dout(dout)
);

endmodule